 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET SAA7130HL PCI video broadcast decoder Product specification 2002 Apr 23 Philips Semiconductors Product specification PCI video broadcast decoder CONTENTS 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 3 4 5 6 6.1 6.2 6.3 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 8.1 8.2 9 10 11 FEATURES PCI and DMA bus mastering TV video decoder and video scaling Peripheral interface General GENERAL DESCRIPTION Introduction Overview of TV decoders with PCI bridge Related documents QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING Pins sorted by number Pins grouped by function Pin description FUNCTIONAL DESCRIPTION Overview of internal functions Application examples Software support PCI interface Analog TV standards Video processing Analog audio pass-through and loop back cable DTV/DVB channel decoding and TS capture Control of peripheral devices BOUNDARY SCAN TEST Initialization of boundary scan circuit Device identification codes LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS 12 13 13.1 13.2 13.3 13.4 13.5 14 15 16 17 PACKAGE OUTLINE SOLDERING SAA7130HL Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2002 Apr 23 2 Philips Semiconductors Product specification PCI video broadcast decoder 1 1.1 FEATURES PCI and DMA bus mastering SAA7130HL * PCI 2.2 compliant including full Advanced Configuration and Power Interface (ACPI) * System vendor ID, etc. via EEPROM * Hardware support for virtual addressing by MMU * DMA bus master write for video, VBI and TS * Configurable PCI FIFOs, graceful overflow * Packed and planar video formats, overlay clipping. 1.2 TV video decoder and video scaling 1.5 General * Package: LQFP128 * Power supply: 3.3 V only * Power consumption of typical application: 1 W * Power-down state (D3-hot): <20 mW * All interface signals 5 V tolerant * Reference designs available * SDK for Windows (95, 98, NT, 2000 and XP), Video for Windows (VfW) and Windows Driver Model (WDM). 2 GENERAL DESCRIPTION * All-standards TV decoder: NTSC, PAL and SECAM * Five analog video inputs: CVBS and S-video * Video digitizing by two 9-bit ADCs at 27 MHz * Sampling according ITU-R BT.601 with 720 pixels/line * Adaptive comb filter for NTSC and PAL, also operating for non-standard signals * Automatic TV standard detection * Three level Macrovision copy protection detection according to Macrovision Detect specification Revision 1 * Control of brightness, contrast, saturation and hue * Versatile filter bandwidth selection * Horizontal and vertical downscaling or zoom * Adaptive anti-alias filtering * Capture of raw VBI samples * Two alternating settings for active video scaling * Output in YUV and RGB * Gamma compensation, black stretching. 1.3 TV audio I/O The SAA7130HL is a single chip solution to digitize and decode video, and capture it through the PCI-bus. Special means are incorporated to maintain the synchronization of audio to video. The device offers versatile peripheral interfaces (GPIO), that support various extended applications, e.g. analog audio pass-through for loop back cable to the sound card, or capture of DTV and DVB transport streams, such as Vestigial Side Band (VSB), Orthogonal Frequency Division Multiplexing (OFDM) and Quadrature Amplitude Modulation (QAM) decoded digital television standards (see Fig.1). * Integrated analog audio pass-through for analog audio loop back cable to sound card. 1.4 * Peripheral interface master interface: 3.3 and 5 V I2C-bus * Digital video output: ITU and VIP formats * TS input: serial or parallel * General purpose I/O, e.g. for strapping and interrupt * Propagate reset and ACPI state D3-hot. 2002 Apr 23 3 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth I 2C-bus TV TUNER: * CABLE * TERRESTRIAL * SATELLITE IF-PLL: * DVB * ATV SIF DTV DVB DIGITAL CHANNEL DECODER: * VSB * QAM * OFDM I 2C-BUS EEPROM AUDIO DECODER: * BTSC audio L/R CVBS S-video audio I/O line-in line-out CVBS AF (mono) TS ENCODER: * MPEG2 I 2S-bus DECODER FOR TV VIDEO WITH TS INTERFACE AND DMA MASTER INTO PCI-BUS ITU656 SAA7130HL MHC169 PCI-bus Fig.1 Application diagram for capturing live TV video in the PC, with optional extensions for enhanced DTV and DVB capture. 2.1 Introduction The PCI video broadcast decoder SAA7130HL is a highly integrated, low cost and solid foundation for TV capture in the PC, for analog TV and digital video broadcast. The various multimedia data types are transported over the PCI-bus by bus-master-write, to optimum exploit the streaming capabilities of a modern host based system. Legacy requirements are also taken care of. The SAA7130HL meets the requirements of PC Design Guides 98/99 and 2001 and is PCI 2.2 and Advanced Configuration and Power Interface (ACPI) compliant. The analog video is sampled by 9-bit ADCs, decoded by a multi-line adaptive comb filter and scaled horizontally, vertically and by field rate. Multiple video output formats (YUV and RGB) are available, including packed and planar, gamma-compensated or black-stretched. Audio is routed as an analog signal via the loop back cable to the sound card. The SAA7130HL provides a versatile peripheral interface to support system extensions, e.g. MPEG encoding for time shift viewing, or DSP applications for audio enhancements. The channel decoder for digital video broadcast reception (ATSC or DVB) can re-use the integrated video ADCs. The Transport Stream (TS) is collected by a tailored interface and pumped through the PCI-bus to the system memory in well-defined buffer structures. Various internal events, or peripheral status information, can be enabled as an interrupt on the PCI-bus. 2002 Apr 23 4 Philips Semiconductors Product specification PCI video broadcast decoder 2.2 Overview of TV decoders with PCI bridge SAA7130HL A TV decoder family with PCI interfacing has been created to support worldwide TV broadcasting. The pin compatibility of these TV decoders offers the opportunity to support different TV broadcast standards with one PCB layout. Table 1 TV decoder family with PCI interfacing TV DECODER TYPE(1) TV PARAMETER SAA7130HL SAA7133HL SAA7134HL SAA7135HL PCI bridge TV video decoding Video scaling Raw VBI TV sound decoding version DMA channel PAL, NTSC and SECAM 2 dimension and 2 task scaler 27 MHz sampling rate FM A2 and NICAM BTSC (dBx) plus SAP; EIAJ stereo sampling (I2S-bus and DMA) Radio Audio FM radio stereo left and right pass-through stereo sampling (I2S-bus and DMA) video frame locked audio incredible surround Dolby(R) Prologic (note 2) virtual Dolby(R) surround volume, bass and treble control Transport stream GPIO serial and parallel TS static I/O pins interrupt input pins I2C-bus multi-master or slave video out Notes 1. X = function available. 2. Dolby is a registered trademark of Dolby Laboratories Licensing Corporation. X 27 4 X X X X 27 4 X X volume only X 27 4 X X X X 32 kHz X X 32 kHz, 44.1 kHz, 48 kHz X X X 32 kHz, 44.1 kHz, 48 kHz X X 32 kHz, 48 kHz 2.2 7 X X X 2.2 7 X X X 2.2 7 X X X X 2.2 7 X X X X X 32 kHz, 48 kHz X X 32 kHz, 44.1 kHz, 48 kHz X X X X X X 27 4 X X 2002 Apr 23 5 Philips Semiconductors Product specification PCI video broadcast decoder 2.3 Related documents SAA7130HL * Data sheets of other devices referred to in this document, e.g: - TDA8961: DTV channel decoder - TD1316: ATV+DVB-T tuner - TDA10045: DVB channel decoder - TDA9886: Analog IF-PLL - TDA9889: Digital IF-PLL. This document describes the functionality and characteristics of the SAA7130HL. Other documents related to the SAA7130HL are: * User manual SAA7130HL/34HL, describing the programmability * Application note SAA7130HL/34HL, pointing out recommendations for system implementation * Demonstration and reference boards, including description, schematics, etc.: - Proteus-Pro: TV capture PCI card for analog TV (standards: B/G, I, D/K and L/L') - Europa: hybrid DVB-T and analog TV capture PCI card for European broadcasting. 3 QUICK REFERENCE DATA SYMBOL VDD Ptot Pstandby Tamb 4 PARAMETER supply voltage total power dissipation standby power dissipation ambient temperature CONDITIONS - D3-hot of ACPI - 0 MIN. 3.0 TYP. 3.3 1.0 - 25 - MAX. 3.6 0.02 70 V UNIT W W C ORDERING INFORMATION TYPE NUMBER PACKAGE NAME LQFP128 DESCRIPTION plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm VERSION SOT425-1 SAA7130HL 2002 Apr 23 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2002 Apr 23 baseband audio inputs left 1 right 1 left 2 right 2 ANALOG NF/AUDIO FRONT-END STEREO BUFFER CV0 CV1 CVBS S-video inputs ANALOG VIDEO FRONT-END 9-BIT VIDEO ADC CV2 CV3 CV4 TS data TS data I 2S GPIO interrupt ANALOG VIDEO FRONT-END 9-BIT VIDEO ADC DIGITAL VIDEO COMB FILTER DECODER 5 Philips Semiconductors VIDEO SCALER PIXEL ENGINE: * MATRIX * GAMMA * FORMAT PCI INTERFACE FIFO DMA handbook, full pagewidth PCI video broadcast decoder BLOCK DIAGRAM AUDIO OUTPUT audio stereo output SAA7130HL PCI-bus 7 TS PARALLEL TS SERIAL STATIC I/O IRQ REGISTER UNIT I 2C-bus ITU656 MHC170 digital data inputs SAA7130HL Product specification Fig.2 Block diagram. Philips Semiconductors Product specification PCI video broadcast decoder 6 PINNING SAA7130HL SYMBOL FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# PAR CBE#1 AD15 AD14 AD13 AD12 VDDD VSSD PCI_CLK PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 8 AD11 AD10 AD9 AD8 CBE#0 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 VDDD VSSD GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 XTALI XTALO VSSD VDDD PIN 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 The SAA7130HL is packaged in a rectangular LQFP (low profile quad flat package) with 128 pins (see Fig.3). In Section 6.1 all the pins are sorted by number. The pin description for the functional groups is given in Tables 2 to 7: * Power supply pins * PCI interface pins * Analog interface pins * Joint Test Action Group (JTAG) test interface pins for boundary scan test * I2C-bus multimaster interface * General purpose interface (pins GPIO) and the main functions. The characteristics of the pin types are detailed in Table 8. 6.1 Pins sorted by number SYMBOL VDDD GNT# REQ# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 CBE#3 IDSEL AD23 AD22 AD21 AD20 AD19 VDDD VSSD AD18 AD17 AD16 CBE#2 2002 Apr 23 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL V_CLK GPIO17 GPIO16 GPIO15 GPIO14 GPIO13 GPIO12 VDDD VSSD GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 GPIO27 GPIO26 GPIO25 SCL SDA VDDD VSSD LEFT2 VDDA LEFT1 VSSA RIGHT1 VREF0 RIGHT2 VREF1 VREF2 OUT_RIGHT OUT_LEFT PROP_RST SIF 2002 Apr 23 PIN 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 9 VREF3 VSSA CV2_C VDDA VREF4 SYMBOL PIN 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 DRCV_Y VSSA CV0_Y VDDA CV1_Y DRCV_C CV3_C VSSA CV4 TRST TCK TMS TDO TDI INT_A PCI_RST# VSSD Philips Semiconductors Product specification PCI video broadcast decoder 6.2 Pins grouped by function Power supply pins PIN 97, 108, 113 and 119 95, 110 and 115 20, 39, 55, 64, 74, 93 and 128 TYPE AG AS VG DESCRIPTION analog ground for integrated analog signal processing SAA7130HL Table 2 SYMBOL VSSA VDDA VSSD analog supply voltage for integrated analog signal processing digital ground for digital circuit, core and I/Os VDDD 1, 19, 38, 54, VS 65, 73 and 92 PCI interface pins; note 1 PIN 40 127 4 to 11, 14 to 18, 21 to 23, 34 to 37, 41 to 44 and 46 to 53 12, 24, 33 and 45 32 25 27 26 29 13 28 3 2 TYPE PI PI digital supply voltage for digital circuit, core and I/Os Table 3 SYMBOL PCI_CLK PCI_RST# AD31 to AD0 DESCRIPTION PCI clock input: reference for all bus transactions, up to 33.33 MHz PCI reset input: will 3-state all PCI pins (active LOW) PIO and multiplexed address and data input or output: bi-directional, 3-state T/S CBE3# to CBE0# PAR FRAME# TRDY# IRDY# STOP# IDSEL DEVSEL# REQ# GNT# PIO and command code input or output: indicates type of requested transaction and T/S byte enable, for byte aligned transactions (active LOW) PIO and parity input or output: driven by the data source, even parity over all pins AD T/S and CBE# PIO and frame input or output: driven by the current bus master (owner), to indicate S/T/S the beginning and duration of a bus transaction (active LOW) PIO and target ready input or output: driven by the addressed target, to indicate S/T/S readiness for requested transaction (active LOW) PIO and initiator ready input or output: driven by the initiator, to indicate readiness to S/T/S continue transaction (active LOW) PIO and stop input or output: target is requesting the master to stop the current S/T/S transaction (active LOW) PI initialization device select input: this input is used to select the SAA7130HL during configuration read and write transactions PIO and device select input or output: driven by the target device, to acknowledge S/T/S address decoding (active LOW) PO PI PCI request output: the SAA7130HL requests master access to PCI-bus (active LOW) PCI grant input: the SAA7130HL is granted to master access PCI-bus (active LOW) 2002 Apr 23 10 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL INT_A PERR# SERR# Note PIN 126 30 31 TYPE PO and O/D DESCRIPTION interrupt A output: this pin is an open-drain interrupt output, conditions assigned by the interrupt register PIO and parity error input or output: the receiving device detects data parity error S/T/S (active LOW) PO and O/D system error output: reports address parity error (active LOW) 1. PCI-bus pins are located on the long side of the package to simplify PCI board layout requirements. Table 4 Analog interface pins; note 1 PIN 62 63 94 95 96 97 98 99 100 101 102 103 104 105 106 107 TYPE CI CO AI AS AI AG AI AR AI - - AO AO AO - AR quartz oscillator output analog audio stereo left 2 input or mono input analog supply voltage (3.3 V) analog audio stereo left 1 input or mono input; default analog pass-through to pin OUT_LEFT after reset analog ground (for audio) analog audio stereo right 1 input or mono input; default analog pass-through to pin OUT_RIGHT after reset analog reference ground for audio Sigma Delta ADC; to be connected directly to analog ground (VSSA) analog audio stereo right 2 input or mono input not connected not connected analog audio stereo right channel output; 1 V (RMS) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 F analog audio stereo left channel output; 1 V (RMS) line-out, feeding the audio loop back cable via a coupling capacitor of 2.2 F analog output for test and debug purpose (active LOW) not connected analog reference voltage for audio FIR-DAC and SCART audio input buffer; to be supported with two parallel capacitors of 47 and 0.1 F to analog ground (VSSA) analog ground composite video input (mode 2) or C input (modes 6 and 8) analog power supply (3.3 V) not connected differential reference connection (for CV0 and CV1); to be supported with a capacitor of 47 nF to analog ground (VSSA) analog ground composite video input (mode 0) or Y input (modes 6 and 8) analog supply voltage (3.3 V) 11 DESCRIPTION quartz oscillator input: 32.11 or 24.576 MHz SYMBOL XTALI XTALO LEFT2 VDDA LEFT1 VSSA RIGHT1 VREF0 RIGHT2 n.c. n.c. OUT_RIGHT OUT_LEFT PROP_RST n.c. VREF3 VSSA CV2_C VDDA n.c. DRCV_Y VSSA CV0_Y VDDA 2002 Apr 23 108 109 110 111 112 113 114 115 AG AI AS - AR AG AI AS Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL CV1_Y DRCV_C CV3_C VSSA CV4 Note PIN 116 117 118 119 120 TYPE AI AR AI AG AI DESCRIPTION composite video input (mode 1) or Y input (modes 7 and 9) differential reference connection (for CV2, CV3 and CV4); to be supported with a capacitor of 47 nF to analog ground (VSSA) composite video input (mode 3) or C input (modes 7 and 9) analog ground composite video input (mode 4) 1. The SAA7130HL offers an interface for analog video and audio signals. The related analog supply pins are included in this table. Table 5 JTAG test interface pins PIN 121 122 123 124 125 I I I O I TYPE DESCRIPTION test reset input: drive LOW for normal operating (active LOW) test clock input: drive LOW for normal operating test mode select input: tie HIGH or let float for normal operating test serial data output: 3-state test serial data input: tie HIGH or let float for normal operating SYMBOL TRST TCK TMS TDO TDI Table 6 I2C-bus multimaster interface PIN 90 91 105 TYPE IO2 IO2 GO DESCRIPTION serial clock output; always available serial data input and output; always available propagate reset and D3-hot output; to peripheral board circuitry SYMBOL SCL SDA PROP_RST 2002 Apr 23 12 Philips Semiconductors Product specification PCI video broadcast decoder Table 7 GPIO pins and functions; note 1 FUNCTION SYMBOL GPIO27 GPIO26 GPIO25 V_CLK GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16 GPIO15 to GIOPIO8 GPIO7 to GPIO0 Note PIN 87 88 89 66 56 57 58 59 60 61 67 68 TYPE GIO GIO GIO GO GIO GIO GIO GIO GIO GIO GIO GIO - - - V_CLK (also gated) HSYNC VSYNC - - - VAUX2 VAUX1 (e.g. VACTIVE) - VP[7:0] for formats: ITU-R BT.656, VMI, VIP (1.1, 2.0), etc. VP extension for 16-bit formats: ZV, VIP-2, DMSD, etc. AUDIO AND VIDEO PORT OUTPUTS - - - - - TS_LOCK (channel decoder locked) TS_S_D (bit-serial data) TS_CLK (<33 MHz) TS_SOP (packet start) - - TS_VAL (valid flag) - TS CAPTURE INPUTS SAA7130HL RAW DTV/DVB OUTPUTS - - - ADC_CLK (out) - - - - X_CLK_IN - ADC_Y[8:1] GPIO R/W R/W R/W - R/W, INT R/W R/W R/W R/W, INT R/W, INT R/W ADC_C[0] (LSB) R/W, INT ADC_Y[0] (LSB) R/W 69 to 72 GIO and 75 to 78 79 to 86 GIO TS_P_D[7:0] (byte-parallel data) ADC_C[8:1] R/W 1. The SAA7130HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions can be selected: a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video, with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes. b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by Start Of Packet (SOP); in byte-parallel or bit-serial protocol. c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB channel decoder. d) GPIO: as default (no other function selected); static (no clock); read and write from or to individually selectable pins; latching `strap' information at system reset time. e) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A). 2002 Apr 23 13 Philips Semiconductors Product specification PCI video broadcast decoder 6.3 Pin description Characteristics of pin types and remarks DESCRIPTION analog ground analog input; video, audio and sound analog output analog reference support pin analog supply voltage (3.3 V) CMOS input; 3.3 V level (not 5 V tolerant) CMOS output; 3.3 V level (not 5 V tolerant) digital input (GPIO); 3.3 V level (5 V tolerant) digital input/output (GPIO); 3.3 V level (5 V tolerant) digital output (GPIO); 3.3 V level (5 V tolerant) JTAG test input SAA7130HL Table 8 PIN TYPE AG AI AO AR AS CI CO GI GIO GO I IO2 O O/D PI PIO PO S/T/S T/S VG VS With overscore or # digital input and output of the I2C-bus interface; 3.3 and 5 V compatible, auto-adapting JTAG test output open-drain output (for PCI-bus); multiple clients can drive LOW at the same time, wired-OR, floating back to 3-state over several clock cycles input according to PCI-bus requirements input and output according to PCI-bus requirements output according to PCI-bus requirements sustained 3-state (for PCI-bus); previous owner drives HIGH for one clock cycle before leaving to 3-state 3-state I/O (for PCI-bus); bi-directional ground for digital supply supply voltage (3.3 V) this pin or `signal' is active LOW, i.e. the function is `true' if the logic level is LOW 2002 Apr 23 14 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL 105 PROP_RST 104 OUT_LEFT 128 VSSD 127 PCI_RST# handbook, full pagewidth 103 OUT_RIGHT 102 n.c. 101 n.c. 100 RIGHT2 99 VREF0 98 RIGHT1 97 VSSA 96 LEFT1 95 VDDA 94 LEFT2 93 VSSD 92 VDDD 91 SDA 90 SCL 89 GPIO25 88 GPIO26 87 GPIO27 86 GPIO0 85 GPIO1 84 GPIO2 83 GPIO3 82 GPIO4 81 GPIO5 80 GPIO6 79 GPIO7 78 GPIO8 77 GPIO9 76 GPIO10 75 GPIO11 74 VSSD 73 VDDD 72 GPIO12 71 GPIO13 70 GPIO14 69 GPIO15 68 GPIO16 67 GPIO17 66 V_CLK 65 VDDD VSSD 64 117 DRCV_C 113 VSSA 112 DRCV_Y 108 VSSA 107 VREF3 GPIO20 59 GPIO19 60 119 VSSA 118 CV3_C 110 VDDA 109 CV2_C 116 CV1_Y 115 VDDA 114 CV0_Y 126 INT_A 121 TRST 123 TMS 124 TDO 122 TCK 120 CV4 111 n.c. VDDD GNT# REQ# AD31 AD30 AD29 AD28 AD27 AD26 1 2 3 4 5 6 7 8 9 AD25 10 AD24 11 CBE#3 12 IDSEL 13 AD23 14 AD22 15 AD21 16 AD20 17 AD19 18 VDDD 19 VSSD 20 AD18 21 AD17 22 AD16 23 CBE#2 24 FRAME# 25 IRDY# 26 TRDY# 27 DEVSEL# 28 STOP# 29 PERR# 30 SERR# 31 PAR 32 CBE#1 33 AD15 34 AD14 35 AD13 36 AD12 37 VDDD 38 VSSD 39 PCI_CLK 40 AD11 41 AD10 42 AD9 43 AD8 44 CBE#0 45 AD7 46 AD6 47 AD5 48 AD4 49 AD3 50 AD2 51 AD1 52 AD0 53 VDDD 54 VSSD 55 GPIO23 56 GPIO22 57 GPIO21 58 GPIO18 61 XTALI 62 XTALO 63 SAA7130HL 106 n.c. 125 TDI MHC168 Fig.3 Pin configuration. 2002 Apr 23 15 Philips Semiconductors Product specification PCI video broadcast decoder 7 7.1 FUNCTIONAL DESCRIPTION Overview of internal functions SAA7130HL The SAA7130HL is able to capture TV signals over the PCI-bus in personal computers by a single chip (see Fig.4). handbook, full pagewidth GPIO digital video output I 2C-bus reset transport stream input stereo output stereo input 1 stereo input 2 5 analog video inputs INPUT SELECTION CLAMP AND GAIN CONTROL 9-BIT ADC 9-BIT ADC VIDEO PORT (DIGITAL) I 2C-BUS INTERFACE DTV-TS p/s I 2S-BUS INPUT ANALOG AUDIO I/O PASS-THROUGH (DEFAULT) DECODER (NTSC, PAL, SECAM) LLC ADAPTIVE COMB FILTER PROPAGATE RESET VIDEO SCALER MATRIX 3-D GAMMA RAW VBI FORMAT PROGRAM PROGRAM SET SET VIDEO FIFOS DMA CONTROL TS FIFOS DMA CONTROL SAA7130HL BOUNDARY SCAN TEST OSCILLATOR PCI-BUS INTERFACE ACPI POWER MANAGEMENT MHC171 PCI-bus test crystal Fig.4 Functional block diagram. 2002 Apr 23 16 Philips Semiconductors Product specification PCI video broadcast decoder The SAA7130HL incorporates two 9-bit video ADCs and the entire decoding circuitry of any analog TV signal: NTSC, PAL and SECAM, including non-standard signals, such as playback from a VCR. The adaptive multi-line comb filter provides superb picture quality, component separation, sharpness and high bandwidth. The video stream can be cropped and scaled to the needs of the application. Scaling down as well as zooming up is supported in the horizontal and vertical direction, and an adaptive filter algorithm prevents aliasing artifacts. With the acquisition unit of the scaler two different `tasks' can be defined, e.g. to capture video to the CPU for compression, and write video to the screen from the same video source but with different resolution, colour format and frame rate. The SAA7130HL incorporates analog audio pass-through and support for the analog audio loop back cable to the sound card function. The decoded video streams are fed to the PCI-bus, and are also applied to a peripheral streaming interface, in ITU, VIP or VMI format. A possible application extension is on-board hardware MPEG compression, or other feature processing. The compressed data is fed back through the peripheral interface, in parallel or serial format, to be captured by the system memory through the PCI-bus. The Transport Stream (TS) from a DTV/DVB channel decoder can be captured through the peripheral interface in the same way. Video and transport streams are collected in a configurable FIFO with a total capacity of 1 kbyte. The DMA controller monitors the FIFO filling degree and master-writes the audio and video stream to the associated DMA channel. The virtual memory address space (from OS) is translated into physical (bus) addresses by the on-chip hardware Memory Management Unit (MMU). The application of the SAA7130HL is supported by reference designs and a set of drivers for the Windows operating system (Video for Windows and Windows Driver Model compliant). 7.2 Application examples SAA7130HL The SAA7130HL enables PC TV capture applications both on the PC mother board and on PCI add-on TV capture cards. Figures 5 and 6 illustrate some examples of add-on card applications. Figure 5 shows the basic application to capture video from analog TV sources. The proposed tuner types incorporate the RF tuning function and the IF downconversion. Usually the IF downconversion stage also includes a single channel and analog sound FM demodulator. The Philips tuner FI1216MK2 is dedicated to the 50 Hz system B/G standard as used in Europe. The FI1236MK2 is the comparable type for the 60 Hz system M standard for the USA. Both types are suited for terrestrial broadcast and for cable reception. The tuner provides composite video and baseband audio as mono or `multiplexed' (mpx) in case of BTSC. These analog video and sound signals are fed to the appropriate input pins of the SAA7130HL. Further analog video input signals, CVBS and/or Y-C, can be connected via the board back-panel, or the separate front connectors, e.g. from a camcorder. Accompanying stereo audio signals can also be fed to the SAA7130HL. Video is digitized and decoded to YUV. The digital streams are pumped via DMA into the PCI memory space. The SAA7130HL incorporates means for legacy analog audio signal routing. The analog audio input signal is fed via an analog audio loop back cable into the line-in of a legacy sound card. An external audio signal, that would have otherwise connected directly to the sound card, is now routed through the SAA7130HL. This analog pass-through is enabled as default by a system reset, i.e. without any driver involvement and before system set-up. During the power-up procedure, the SAA7130HL will investigate the on-board EEPROM to load the board specific system vendor ID and board version ID into the related places of the PCI configuration space. The board vendor can store other board specific data in the EEPROM that is accessible via the I2C-bus. 2002 Apr 23 17 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth TV CAPTURE PCI CARD TV cable or terrestrial TV TUNER AND IF-PLL I 2C-bus CVBS AF sound (mono) analog audio loop back cable CVBS S-video audio line-in DMA MASTER INTO PCI DECODER FOR TV VIDEO SOUND CARD I 2C-BUS EEPROM SYSTEM VENDOR ID SAA7130HL PCI-bus: digital video, raw VBI, TS SOUTH BRIDGE ISA SYSTEM MEMORY NORTH BRIDGE AGP VGA AND LOCAL MEMORY FSB CPU AND CACHE MEMORY MHC172 Fig.5 TV mono capture card. 2002 Apr 23 18 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth HYBRID TV CAPTURE PCI CARD ATV cable or terrestrial and DVB terrestrial IF ANALOG IF-PLL CVBS AF TS IF TV TUNER DIGITAL IF-PLL DVB-T CHANNEL DECODER CVBS S-video audio line-in DMA MASTER INTO PCI DECODER FOR TV VIDEO analog audio loop back cable I 2C-bus I 2C-BUS EEPROM SYSTEM VENDOR ID SOUND CARD SAA7130HL PCI-bus: digital video, raw VBI, TS SOUTH BRIDGE ISA SYSTEM MEMORY NORTH BRIDGE AGP VGA AND LOCAL MEMORY FSB CPU AND CACHE MEMORY MHC173 Fig.6 Hybrid TV capture board for digital TV (DVB-T) and analog TV reception. Figure 6 shows an application extension with a hybrid TV tuner front-end and digital terrestrial channel decoding for DTV-T. The single-conversion tuner TD1316 provides two dedicated IF signals for the analog IF-PLL (TDA9886) and the digital IF-PLL (TDA9889). The CVBS (video) and AUD (audio, mono) output signals of the analog IF-PLL can be routed to one of the video inputs and the audio (left or right) input of the SAA7130HL for analog video decoding and direct audio streaming to the sound card. On the other hand, the 2nd IF signal of the digital IF-PLL is fed directly to the interface of the channel decoder (TDA10045), which decodes the signal into a digital DVB-T Transport Stream (TS). 2002 Apr 23 19 The SAA7130HL captures this TS via the dedicated peripheral interface into the configurable internal FIFO for DMA into the PCI memory space. The packet structure as decoded by the TDA10045 is maintained in a well-defined buffer structure in the system memory, and therefore can easily be sorted (de-multiplexed) by the CPU for proper MPEG decoding. The Broadcast Driver Architecture (BDA) for Windows operating systems supports this type of hybrid TV capture application, sharing one capture board for analog and digital TV reception. Philips Semiconductors Product specification PCI video broadcast decoder 7.3 7.3.1 Software support DEVICE DRIVER SAA7130HL A complex and powerful software packet is provided for the SAA7130HL. This packet includes plug-and-play driver and capture driver installations for all commonly used 32-bit Windows platforms. All platform related drivers support the following: * Video preview and capture interfaces * Audio control and audio capture interfaces * Custom application interface, that enables the development of specialized applications in cases where the published Windows Application Program Interface (API) such as WDM or VfW is not sufficient. Table 9 Microsoft Operation System (MOS) support DRIVER SUPPORT Device access is contained within a VxD. The Video for Windows (VfW) capture driver interface is a 16-bit user-mode interface. Device access is contained in a kernel-mode driver. The VfW capture driver interface is a 32-bit user-mode interface. Device access is contained with a kernel-mode Windows Driver Model (WDM) driver. The capture driver interface is also kernel-mode WDM. The driver is binary-compatible with the Windows 98 driver. The driver is binary-compatible with the Windows 98 driver. The driver is binary-compatible with the Windows 98 driver. MOS Windows 95 Windows NT4 Windows 98 Windows 2000 Windows ME Windows XP 7.3.2 SUPPORTING WDM The WDM driver for Windows 98 and Windows 2000 (see Fig.7) is a kernel-mode driver that implements a Kernel Streaming (KS) filter with output pins for audio, video preview, video capture and VBI, together with a crossbar for input source selection and optional connections for other on-board devices as child drivers. The WDM driver is implemented as a stream class mini-driver. It also exposes the external interfaces to support the user-mode 34API DLL. Custom applications and debug tools will continue to work without the need to load different drivers. handbook, full pagewidth TV TUNER XBAR external video inputs audio inputs transport stream in MHC174 SAA7130HL CAPTURE DRIVER video preview video capture VBI Fig.7 WDM capture driver filters. 2002 Apr 23 20 Philips Semiconductors Product specification PCI video broadcast decoder 7.3.3 SUPPORTING VfW SAA7130HL * Capture transport streams (MPEG data) from a channel decoder chip (OFDM, VSB, QAM) for supporting digital TV applications, or from an on-board MPEG encoder chip that is fed by the video output port of the SAA7130HL * Capture raw VBI sample stream to a stream of buffers over the PCI-bus * Access to the I2C-bus master for controlling other peripheral circuits. The 34API transfers the device driver functionality through a proxy interface to the user-mode. The proxy interface adapts to the different kernel-mode implementations, so that the common 34API can be used on all Windows operating systems in the same way. The SDK for the SAA7130HL contains the detailed description of all software components such as API documentation for streaming, tuner control, dialogues and direct draw control. The provided sample code will introduce the user into working with this interface. All necessary header and library files are provided. The traditional Video for Windows (VfW) interface is supported for Windows 9x and for Windows NT4.0 (see Fig.8). In both cases a 32-bit capture driver based on the SAA713x user-mode API (34API.DLL) controls the video functionality and the user-mode audio driver implementation. The capture driver supports direct draw surfaces for live video and is able to capture video in packed data formats and in planar formats. TV applications such as Intel intercast and Philips teletext are supported by a private VBI extension. In the event that VfW has to be implemented as a 16-bit interface under Windows 9x, a thunk layer is included for connecting the 16-bit interface to the 32-bit capture driver. Old 16-bit applications using VfW are still supported in this way. VidCap (WIN 9x) VidCap32 (WIN NT4.0) 34Vcap16.DLL 34Vcap.DLL 34Vcap32.EXE 34Vcap32.DLL 34API.DLL 34API.DLL VBI extension for intercast, CC, TXT 34W95.VxD MHB994 34W95.VxD 34WDM.SYS 34NT4.SYS MHB995 Fig.8 VfW driver structure. Fig.9 User program interface. 7.3.4 SOFTWARE DEVELOPMENT KIT FOR CUSTOMER RELATED APPLICATIONS In addition to the capture driver, an Application Programmers Interface (API) Dynamic Linked Library (DLL) provides the whole range of functionality to control the device (see Fig.9). This class library is built in c++ and provides methods to: * Capture video into a fixed buffer (including clipping) * Capture video to a stream of buffers over VBI 2002 Apr 23 21 Philips Semiconductors Product specification PCI video broadcast decoder 7.4 7.4.1 PCI interface PCI CONFIGURATION REGISTERS 7.4.2 ACPI AND POWER STATES SAA7130HL The PCI interface of the SAA7130HL complies with the "PCI specification 2.2" and supports power management and Advanced Configuration and Power Interface (ACPI) as required by the "PC Design Guide 2001". The PCI specification defines a structure of the PCI configuration space that is investigated during the boot-up of the system. The configuration registers (see Table 10) hold information essential for plug-and-play, to allow system enumeration and basic device set-up without depending on the device driver, and support association of the proper software driver. Some of the configuration information is hard-wired in the device; some information is loaded during the system start-up. The device vendor ID is hard coded to 11 31H, which is the code for Philips as registered with PCI-SIG. The device ID is hard coded to 71 30H. During power-up, initiated by PCI reset, the SAA7130HL fetches additional system information via the I2C-bus from the on-board EEPROM, to load actual board type specific codes for the system vendor ID, sub-system ID (board version) and ACPI related parameters into the configuration registers. Table 10 PCI configuration registers FUNCTION Device vendor ID Device ID Revision ID Class code Memory address space required System (board) vendor ID Sub-system (board version) ID Note 1. X = don't care. REGISTER ADDRESS (HEX) 00 and 01 02 and 03 08 09 to 0B 10 to 13 2C and 2D 2E and 2F The "PCI specification 2.2" requires support of "Advanced Configuration and Power Interface specification 1.0" (ACPI); more details are defined in the "PCI Power Management Specification 1.0". The power management capabilities and power states are reported in the extended configuration space. The main purpose of ACPI and PCI power management is to tailor the power consumption of the device to the actual needs. The SAA7130HL supports all four ACPI device power states (see Table 11). The pin PROP_RST of the peripheral interface is switched active LOW during the PCI reset procedure, and for the duration of the D3-hot state. Peripheral devices on board of the add-on card should use the level of this signal PROP_RST to switch themselves in any power-save mode (e.g. disable device) and reset to default settings on the rising edge of signal PROP_RST. The length of signal PROP_RST is programmable. VALUE (HEX) 11 31 71 30 00 04 80 00 XXXXXXXX XXXXXXXX XXXXXX00 00000000 (b) loaded from EEPROM loaded from EEPROM REMARK for Philips for SAA7130HL or higher multimedia 1 kbyte; note 1 2002 Apr 23 22 Philips Semiconductors Product specification PCI video broadcast decoder Table 11 Power management table POWER STATE D0 DESCRIPTION SAA7130HL Normal operation: all functions accessible and programmable. The default setting after reset and before driver interaction (D0 un-initialized) switches most of the circuitry of the SAA7130HL into the power-down mode, effectively such as D3-hot. First step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. Most of the circuitry of the SAA7130HL is disabled with exception of the crystal and real-time clock oscillators, so that a quick recovery from D1 to D0 is possible. Second step of reduced power consumption: no functional operation; program registers are not accessible, but content is maintained. All functional circuitry of the SAA7130HL is disabled, including the crystal and clock oscillators. Lowest power consumption: no functional operation. The content of the programming registers gets lost and is set to default values when returning to D0. DMA AND CONFIGURABLE FIFO The association between the virtual (logic) address space and the fragmented physical address space is defined in page tables (system files); see Fig.10. The SAA7130HL incorporates hardware support (MMU) to translate virtual to physical addresses on the fly, by investigating the related page table information. This hardware support reduces the demand for real-time software interaction and interrupt requests, and therefore saves system resources. 7.4.5 STATUS AND INTERRUPTS ON PCI-BUS D1 D2 D3-hot 7.4.3 The SAA7130HL supports seven DMA channels to master-write captured active video, raw VBI and DTV/DVB Transport Streams (TS) into the PCI memory. Each DMA channel contains inherently the definition of two buffers, e.g. for odd and even fields in case of interlaced video. The DMA channels share in time and space one common FIFO pool of 256 Dwords (1024 bytes) total. It is freely configurable how much FIFO capacity can be associated with which DMA channel. Furthermore, a preferred minimum burst length can be programmed, i.e. the amount of data to be collected before the request for the PCI-bus is issued. This means that latency behaviour per DMA channel can be tailored and optimized for a given application. In the event that a FIFO of a certain channel overflows due to latency conflict on the bus, graceful overflow recovery is applied. The mount of data that gets lost because it could not be transmitted, is monitored (counted) and the PCI-bus address pointer is incremented accordingly. Thus new data will be written to the correct memory place, after the latency conflict is resolved. 7.4.4 VIRTUAL AND PHYSICAL ADDRESSING The SAA7130HL provides a set of status information about internal signal processing, video standard detection, peripheral inputs and outputs (pins GPIO) and behaviour on the PCI-bus. This status information can be conditionally enabled to raise an interrupt on the PCI-bus, e.g. completion of a certain DMA channel or buffer, or change in a detected TV standard, or the state of peripheral devices. The cause of an issued interrupt is reported in a dedicated register, even if the original condition has changed before the system was able to investigate the interrupt. Most operating systems allocate memory to requesting applications for DMA as continuous ranges in virtual address space. The data flow over the PCI-bus points to physical addresses, usually not continuous and split in pages of 4 kbytes (Intel architecture, most UNIX systems, Power PC). 2002 Apr 23 23 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL physical memory handbook, full pagewidth 00000H real-time streams FIFO POOL 00007H DMA DEFINITIONS (VIRTUAL ADDRESS SPACE) page table 000H 0000FH 00001000H 00008000H 00009000H 0000A000H 0000D000H 00011000H 00014000H 00016000H 0001E000H DMA ADDRESS GENERATION 007H 00017H VIRTUAL TO PHYSICAL ADDRESS TRANSLATION 015H 0001FH PCI TRANSFER AND CONTROL = allocated memory space = page table physical address space on PCI MHB996 Fig.10 MMU implementation (shown bit width indication is valid for 4 kbytes mode). 2002 Apr 23 24 Philips Semiconductors Product specification PCI video broadcast decoder 7.5 Analog TV standards SAA7130HL Video signals from local consumer equipment, e.g. VCR, camcorder, camera, game console, or even DVD player, often do not follow the standard specification very accurately. Playback from video tape cannot be expected to maintain correct timing, especially not during feature mode (fast forward, etc.). Tables 12 to 14 list some characteristics of the various TV standards. The SAA7130HL decodes all colour TV standards and non-standard signals as generated by video tape recorders e.g. automatic video standard detection can be applied, with preference options for certain standards, or the decoder can be forced to a dedicated standard. Analog TV signals are described in three categories of standards: * Basic TV systems: defining frame rate, number of lines per field, levels of synchronization signals, blanking, black and white, signal bandwidth and the RF modulation scheme * Colour transmission: defining colour coding and modulation method * Sound and stereo: defining coding for transmission. TV signals that are broadcasted usually conform fairly accurately to the standards. Transmission over the air or through a cable can distort the signal with noise, echoes, crosstalk or other disturbances. Table 12 Overview of basic TV standards MAIN PARAMETERS RF channel width Video bandwidth 1st sound carrier Field rate Lines per frame Line frequency ITU clocks per line Sync, set-up level Gamma correction Associated colour TV standards Associated stereo TV sound systems Country examples STANDARD UNIT M 6 4.2 4.5, FM 59.94006 525 15.734 1716 -40, 7.5 2.2 NTSC, PAL BTSC, EIAJ, A2 USA, Japan, Brazil N 6 4.2 4.5, FM 50 625 15.625 1728 -40, 7.5 2.2 PAL BTSC Argentina B 7 5 5.5, FM 50 625 15.625 1728 -43, 0 2.8 PAL dual FM, A2 part of Europe, Australia G, H 7 5 5.5, FM 50 625 15.625 1728 -43, 0 2.8 PAL NICAM Spain, Malaysia, Singapore I 8 5.5 6.0, FM 50 625 15.625 1728 -43, 0 2.8 PAL NICAM UK, Northern Europe D/K 7 6 6.5, FM 50 625 15.625 1728 -43, 0 2.8 SECAM, PAL NICAM, A2 China, Eastern Europe L 8 6 6.5, AM 50 625 15.625 1728 -43, 0 2.8 SECAM NICAM France, Eastern Europe MHz MHz MHz Hz - kHz - IRE - - - - 2002 Apr 23 25 Philips Semiconductors Product specification PCI video broadcast decoder Table 13 TV system colour standards MAIN PARAMETERS Field rate Lines per frame Chrominance subcarrier fsc to H ratio fsc offset (PAL) Alternating phase Country examples NTSC M 59.94 525 3.580 227.5 - no USA, Japan, Asia-Pacific PAL M 59.94 525 3.576 227.25 - yes Brazil PAL N 50 625 3.582 229.25 50 yes Middle and South America PAL BGHID 50 625 4.434 283.75 50 yes Europe, Commonwealth, China 4.406 282 - - SECAM LDGHK 50 625 4.250 272 - - SAA7130HL PAL 4.4 (60 Hz) 60 525 4.434 n.a. n.a. yes VCR transcoding NTSC-tape to PAL UNIT Hz MHz Hz France, Eastern Europe, Africa, Middle East Table 14 TV stereo sound standards MAIN PARAMETERS Stereo coding scheme 2nd language Sound IF M, N B, G, H I DK (1) DK (2) DK (3) L De-emphasis Audio bandwidth Country examples 4.5 FM 5.5 FM 6.0 FM 6.5 FM 6.5 FM 6.5 FM 6.5 AM 75 15 worldwide 4.5 not used not used not used - - not used 75, dBx 15 USA, South America 4.5 not used not used not used - - not used 50 15 Japan ANALOG SYSTEMS MONO - - BTSC AM mono SAP on internal FM EIAJ FM as alternative to stereo A2 (DUAL FM) 2nd FM carrier as alternative to stereo 1st 4.5 5.5 not used 6.5 - - not used 15 2nd 4.724 5.742 not used 6.742 6.258 5.742 not used 50 or 75 DIGITAL CODING UNIT NICAM DQPSK on FM mono on 1st carrier 1st not used 5.5 6.0 6.5 - - 6.5 15 50 or J17 2nd not used 5.850 6.552 5.850 - - 5.850 MHz MHz MHz MHz MHz MHz MHz s kHz internal carrier (mpx) 2-Carrier Systems (2CS) part of Europe, Korea part of Europe, China 2002 Apr 23 26 Philips Semiconductors Product specification PCI video broadcast decoder 7.6 7.6.1 Video processing ANALOG VIDEO INPUTS SAA7130HL The video decoder of the SAA7130HL incorporates an automatic standard detection, that does not only distinguish between 50 and 60 Hz systems, but also determines the colour standard of the video input signal. Various preferences (`look first') for automatic standard detection can be chosen, or a selected standard can be forced directly. 7.6.4 ADAPTIVE COMB FILTER The SAA7130HL provides five analog video input pins: * Composite video signals (CVBS), from tuner or external source * S-video signals (pairs of Y-C), e.g. from camcorder * DTV/DVB `low-IF' signal, from an appropriate DTV or combi-tuner. Analog anti-alias filters are integrated on chip and therefore, no external filters are required. The device also contains automatic clamp and gain control for the video input signals, to ensure optimum utilization of the ADC conversion range. The nominal video signal amplitude is 1 V (p-p) and the gain control can adapt deviating signal levels in the range of +3 dB to -6 dB. The video inputs are digitized by two ADCs of 9-bit resolution, with a sampling rate of nominal 27 MHz (the line-locked clock) for analog video signals. 7.6.2 VIDEO SYNCHRONIZATION AND LINE-LOCKED CLOCK The SAA7130HL applies adaptive comb filter techniques to improve the separation of luminance and chrominance components in comparison to the separation by a chroma notch filter, as used in traditional TV colour decoder technology. The comb filter compares the signals of neighbouring lines, taking into account the phase shift of the chroma subcarrier from line to line. For NTSC the signal from three adjacent lines are investigated, and in the event of PAL the comb filter taps are spread over four lines. Comb filtering achieves higher luminance bandwidth, resulting in sharper picture and detailed resolution. Comb filtering further minimizes colour crosstalk artifacts, which would otherwise produce erroneous colours on detailed luminance structures. The comb filter as implemented in the SAA7130HL is adaptive in two ways: * Adaptive to transitions in the picture content * Adaptive to non-standard signals (e.g. VCR). The integrated digital delay lines are always exactly correct, due to the applied unique line-locked sampling scheme (LLC). Therefore the comb filter does not need to be switched off for non-standard signals and remains operating continuously. 7.6.5 MACROVISION DETECTION The SAA7130HL recovers horizontal and vertical synchronization signals from the selected video input signal, even under extremely adverse conditions and signal distortions. Such distortions are `noise', static or dynamic echoes from broadcast over air, crosstalk from neighbouring channels or power lines (hum), cable reflections, time base errors from video tape play-back and non-standard signal levels from consumer type video equipment (e.g. cameras, DVD). The heart of this TV synchronization system is the generation of the Line-Locked Clock (LLC) of nominal 27 MHz, as defined by ITU-R BT.601. The LLC ensures orthogonal sampling, and always provides a regular pattern of synchronization signals, that is a fixed and well defined number of clock pulses per line. This is important for further video processing devices connected to the peripheral video port (pins GPIO). It is very effective to run under the LLC of 27 MHz, especially for on-board hardware MPEG encoding devices, since MPEG is defined on this clock and sampling frequency. 7.6.3 VIDEO DECODING AND AUTOMATIC STANDARD DETECTION The SAA7130HL incorporates colour decoding for any analog TV signal. All colour TV standards and flavours of NTSC, PAL, SECAM and non-standard signals (VCR) are automatically recognized and decoded into luminance and chrominance components, i.e. Y-CB-CR, also known as YUV. 2002 Apr 23 27 The SAA7130HL detects if the decoded video signal is copy protected by the Macrovision system. The detection logic distinguishes the three levels of the copy protection as defined in rev. 7.01, and are reported as status information. The decoded video stream is not effected directly, but application software and Operation System (OS) has to ensure, that this video stream maintains tagged as `copy protected', and such video signal would leave the system only with the reinforced copy protection. The multi-level Macrovision detection on the video capture side supports proper TV re-encoding on the output point, e.g. by Philips TV encoders SAA712x or SAA7102. Philips Semiconductors Product specification PCI video broadcast decoder 7.6.6 VIDEO SCALING SAA7130HL The scaling acquisition definition also includes cropping, frame rate reduction, and defines the amount of pixels and lines to be transported through DMA over the PCI-bus. Two programming pages are available to enable re-programming of the scaler in the `shadow' of the running processing, without holding or disturbing the flow of the video stream. Alternatively, the two programming pages can be applied to support two video destinations or applications with different scaler settings, e.g. firstly to capture video to CPU for compression (storage, video phone), and secondly to pre-view the picture on the monitor screen. A separate scaling region is dedicated to capture raw VBI samples, with a specific sampling rate, and be written into its own DMA channel. The SAA7130HL incorporates a filter and processing unit to downscale or upscale the video picture in the horizontal and vertical dimension, and in frame rate (see Figs 11 and 12). The phase accuracy of the re-sampling process is 164 of the original sample distance. This is equivalent to a clock jitter of less than 1 ns. The filter depth of the anti-alias filter adapts to the scaling ratio, from 10 taps horizontally for scaling ratios close to 1 : 1, to up to 74 taps for an icon sized video picture. Most video capture applications will typically require for downscaling. But some zooming is required for conversion of ITU sampling to square pixel (SQP), or to convert the 240 lines of an NTSC field to 288 lines to comply with CCITT video phone formats. handbook, full pagewidth VBI first sample 1st field (odd, FID = 0) VBI region, raw samples sample rate VBI last sample VBI DMA 1st buffer (A) 2nd buffer (A) VBI first line VBI last line video region - cropped - scaled scaling active video area 2nd field (even, FID = 1) VBI region, raw samples video first line video region - cropped - scaled scaling sample rate video DMA (A) e.g. interlaced 1st buffer (upper field) 2nd buffer (lower field) video last line active video area MHB997 video first pixel video last pixel The capture acquisition for scaling and DMA has separate programming parameters for VBI and video region and associated DMA channels. Fig.11 Scaler processing with DMA interfacing. 2002 Apr 23 28 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth 1st field (odd, FID = 0) VBI region, raw samples sample rate VBI DMA 1st buffer (A) video region (A) - cropped 2nd buffer (A) scaling 3rd buffer (B) 4th buffer (B) task "A" active video area 2nd field (even, FID = 1) VBI region, raw samples sample rate video region (A) - cropped video DMA (A) e.g. interlaced 1st buffer (upper field) scaling 2nd buffer (lower field) active video area 3rd field (odd, FID = 0) VBI region, raw samples sample rate video region (B) - skipped for field rate reduction video DMA (B) e.g. single FID task "B" active video area 4th field (even, FID = 1) VBI region, raw samples sample rate 1st buffer 2nd buffer (next frame) video region - scaled down CIF MHB998 scaling active video area alternating processing task A/B Two video capture tasks can be processed in an alternating manner, without need to reprogram any scaling parameters or DMA definition. Fig.12 Scaler task processing with DMA interfacing. 2002 Apr 23 29 Philips Semiconductors Product specification PCI video broadcast decoder 7.6.7 VBI DATA SAA7130HL The video components do not use the entire number range, but leave some margin for overshoots and intermediate values during processing. For the raw VBI samples there is no official specification how to code, but it is common practice to reserve the lower quarter of the number range for the sync, and to leave some room for overmodulation beyond the nominal white amplitude (see Fig.14). The automatic clamp and gain control at the video input, together with the automatic chroma gain control of the SAA7130HL, ensures that the video components stream at the output comply to the standard levels. Beyond that additional brightness, contrast, saturation and hue control can be applied to satisfy special needs of a given application. The raw VBI samples can be adjusted independent of the active video. The SAA7130HL incorporates the YUV-to-RGB matrix (optional), the RGB-to-YUV matrix and a three channel look-up table in between (see Fig.15). Under nominal settings, the RGB space will use the same number range as defined by the ITU and shown in Fig.13a for luminance, between 16 and 235. As graphic related applications are based on full-scale RGB, i.e. 0 to 255, the range can be stretched by applying appropriate brightness, contrast and saturation values. The look-up table supports gamma correction (freely definable), and allows other non-linear signal transformation such as black stretching. The analog TV signal applies a quite strong gamma pre-compensation (2.2 for NTSC and 2.8 for PAL). As computer monitors exhibit a gamma (around 2.5), the difference between gamma pre-compensation and actual screen gamma has to be corrected, to achieve best contrast and colour impression. The SAA7130HL offers a multitude of formats to write video streams over the PCI-bus: YUV and RGB colour space, 15-bit, 16-bit, 24-bit and 32-bit representation, packed and planar formats. For legacy requirements (VfW) a clipping procedure is implemented, that allows the definition of 8 overlay rectangles. This process can alternatively be used to associate `alpha' values to the video pixels. The Vertical Blanking Interval (VBI) is often utilized to transport data over analog video broadcast. Such data can closely relate to the actual video stream, or just be general data (e.g. news). Some examples for VBI data types are: * Closed Caption (CC) for the hearing impaired (CC, on line 21 of first field) * Intercast data [in US coded in North-American Broadcast Text System (NABTS) format, in Europe in World Standard Teletext (WST)], to transmit internet related services, optionally associated with actual video program content * Teletext, transporting news services and broadcast related information, Electronic Program Guide (EPG), widely used in Europe (coded in WST format) * EPG, broadcaster specific program and schedule information, sometimes with proprietary coding scheme (pay service), usually carried on NABTS, WST, Video Programming Service (VPS), or proprietary data coding format * Video Time Codes (VTC) as inserted in camcorders e.g. use for video editing * Copy Guard Management System (CGMS) codes, to indicate copy protected video material, sometimes combined with format information [Wide Screen Signalling (WSS)]. This information is coded in the unused lines of the vertical blanking interval, between the vertical sync pulse and the active visible video picture. So-called full-field data transmission is also possible, utilizing all video lines for data coding. The SAA7130HL supports capture of VBI data by the definition of a VBI region to be captured as raw VBI samples, that will be sliced and decoded by software on the host CPU. The raw sample stream is taken directly from the ADC and is not processed or filtered by the video decoder. The sampling rate of raw VBI can be adjusted to the needs of the data slicing software. 7.6.8 SIGNAL LEVELS AND COLOUR SPACE Analog TV video signals are decoded into its components luminance and colour difference signals (YUV) or in its digital form Y-CB-CR. ITU-R BT.601 defines 720 pixels along the line (corresponding to a sampling rate of 27 MHz divided by two), and a certain relationship from level to number range (see Fig.13). 2002 Apr 23 30 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL +255 +235 white +255 +240 +212 blue 100% blue 75% +255 +240 +212 red 100% red 75% +128 LUMINANCE 100% +128 U-COMPONENT colourless +128 V-COMPONENT colourless +44 +16 0 black +16 0 yellow 75% yellow 100% +44 +16 0 cyan 75% cyan 100% MGC634 a. Y output range. b. U output range (CB). c. V output range (CR). Fig.13 Nominal digital levels for YUV (Y-CB-CR) in accordance with ITU-R BT.601. +255 +209 white +255 +199 white LUMINANCE LUMINANCE +71 +60 SYNC 1 black black shoulder +60 SYNC black shoulder = black sync bottom 1 sync bottom MGD700 a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. Fig.14 Nominal digital levels for CVBS and raw VBI samples. 2002 Apr 23 31 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth three channel non-linear transformation Y YUV to RGB matrix R R RGB to YUV matrix Y U G G U V B B V MHB999 Fig.15 Colour space conversion and look-up table. 7.6.9 VIDEO PORT, ITU AND VIP CODES The decoded and/or scaled video stream can be captured via PCI-DMA to the system memory, and/or can be made available locally through the video side port (VP), using some of the GPIO pins. Two types of applications are intended: * Streaming real-time video to a video side port at the VGA card, e.g. via ribbon cable over the top * Feeding video stream to a local MPEG compression device on the same PCI board, e.g. for time shift viewing applications. The video port of the SAA7130HL supports the following 8 and 16-bit wide YUV video signalling standards (see Table 7): * VMI: 8-bit wide data stream, clocked by LLC = 27 MHz, with discrete sync signals HSYNC, VSYNC and VACTIVE * ITU-R BT.656, parallel: 8-bit wide data stream, clocked by LLC = 27 MHz, synchronization coded in SAV and EAV codes * VIP 1.1 and 2.0: 8-bit or 16-bit wide data stream, clocked by LLC = 27 MHz, synchronization coded in SAV and EAV codes (with VIP extensions) * Zoom Video (ZV): 16-bit wide pixel stream, clocked by LLC/2 = 13.5 MHz, with discrete sync signals HSYNC and VSYNC * ITU-R BT.601 direct (DMSD): 16-bit wide pixel stream, clocked by LLC = 27 MHz, with discrete sync signals HSYNC, VSYNC/FID and CREF * Raw DTV/DVB sample stream: 9-bit wide data, clocked with a copy of signal X_CLK_IN. The VIP standard can transport scaled video and discontinuous data stream by allowing the insertion of `00' as marker for empty clock cycles. For the other video port standards, a data valid flag or gated clock can be applied. 7.7 Analog audio pass-through and loop back cable Most operating systems are prepared to deal with audio input at only one single entry point, namely at the sound card function. Therefore the sound associated with video has to get routed through the sound card. The SAA7130HL supports analog audio pass-through and the loop back cable on-chip. No external components are required. The audio signal, that was otherwise connected to the sound card line-in, e.g. analog sound from a CD-ROM drive, has to be connected to one of the inputs of the SAA7130HL. By default, after a system reset and without involvement of any driver, this audio signal is passed through to the analog audio output pins, that will feed the loop back cable to the sound card line-in connector. The AV capture driver has to open the default pass-through and switch in the TV sound signal by will. 2002 Apr 23 32 Philips Semiconductors Product specification PCI video broadcast decoder 7.8 DTV/DVB channel decoding and TS capture 7.9.2 PROPAGATE RESET SAA7130HL The SAA7130HL is optimum equipped to support the application extension to capture digital TV signals, e.g. for VSB (ATSC) or DVB (T/C/S). A hybrid TV tuner for analog and digital TV broadcast reception usually provides a DTV signal on low IF, i.e. downconverted into a frequency range from 0 to 10 MHz. Such signals can be fed to one of the 5 video inputs of the SAA7130HL for digitizing. The digital raw DTV is output at the video port, and is sent to the peripheral channel decoder, e.g. TDA8961 for VSB-8 decoding. The channel decoder provides the sampling clock via the external clock input pin X_CLK_IN (up to 36 MHz input clock frequency), and adjusts the signal gain in the tuner or in the video input path in front of the ADC. Alternatively, the low IF DTV/DVB signal could be fed directly to the channel decoder, depending on the capability for digitizing the selected device. The peripheral channel decoder circuitry decodes the digital transmission into bits and bytes, apply error correction etc., and outputs a packed Transport Stream (TS) accompanied by a clock and handshake signals. The SAA7130HL captures the TS in parallel or serial protocol, synchronized by Start Of Packet (SOP), and pumps it via the dedicated DMA into the PCI memory space. The DMA definition supports automatic toggling between two buffers. 7.9 7.9.1 Control of peripheral devices I2C-BUS MASTER The PCI system reset and ACPI power management state D3 is propagated to peripheral devices by the dedicated pin PROP_RST. This signal is switched to active LOW by reset and D3, and is only switched HIGH under control of the device driver `by will'. The intention is that peripheral devices will use signal PROP_RST as Chip-Enable (CE). The peripheral devices should enter a low power consumption state if pin PROP_RST = LOW, and reset into default setting at the rising edge. 7.9.3 GPIO The SAA7130HL offers a set of General Purpose Input/Output (GPIO) pins, to interface to on-board peripheral circuits. These GPIOs are intended to take over dedicated functions: * Digital video port output: 8-bit or 16-bit wide (including raw DTV) * Transport stream input: parallel or serial (also applicable as I2S-bus input) * Peripheral interrupt input: four GPIO pins of the SAA7130HL can be enabled to raise an interrupt on the PCI-bus. By this means, peripheral devices can directly intercept with the device driver on changed status or error conditions. Any GPIO pin that is not used for a dedicated function is available for direct read and write access via the PCI-bus. Any GPIO pin can be selected individually as input or output (masked write). By these means, very tailored interfacing to peripheral devices can be created via the SAA7130HL capture driver running on Windows operating systems. At system reset (PCI reset) all GPIO pins will be set to 3-state and input, and the logic level present on the GPIO pins at that moment will be saved into a special `strap' register. All GPIO pins have an internal pull-down resistor (LOW level), but can be strapped externally with a 4.7 k resistor to the supply voltage (HIGH level). The device driver can investigate the strap register for information about the hardware configuration of a given board. The SAA7130HL incorporates an I2C-bus master to set-up and control peripheral devices such as tuner, DTV/DVB channel decoder, audio DSP co-processors, etc. The I2C-bus interface itself is controlled from the PCI-bus on a command level, reading and writing byte by byte. The actual I2C-bus status is reported (status register) and, as an option, can raise error interrupts on the PCI-bus. At PCI reset time, the I2C-bus master receives board specific information from the on-board EEPROM to update the PCI configuration registers. The I2C-bus interface is multi-master capable and can assume slave operation too. This allows application of the device in the stand-alone mode, i.e. with the PCI-bus not connected. Under the slave mode, all internal programming registers can be reached via the I2C-bus with exception of the PCI configuration space. 2002 Apr 23 33 Philips Semiconductors Product specification PCI video broadcast decoder 8 BOUNDARY SCAN TEST SAA7130HL To solve the power-up reset, the standard specifies that the TAP controller will be forced asynchronously to the TEST_LOGIC_RESET state by setting pin TRST to LOW level. 8.2 Device identification codes The SAA7130HL has built-in logic and five dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). The SAA7130HL follows the "IEEE Std. 1149.1 - Standard Test Access Port and Boundary - Scan Architecture" set by the Joint Test Action Group (JTAG) chaired by Philips. The 5 special pins are: Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and IDCODE are all supported (see Table 15). Details about the JTAG BST-test can be found in the specification "IEEE Std. 1149.1". A file containing the detailed Boundary Scan Description Language (BSDL) description of the SAA7130HL is available on request. 8.1 Initialization of boundary scan circuit When the IDCODE instruction is loaded into the BST instruction register, the identification register will be connected internally between pins TDI and TDO of the IC. The identification register will load a component specific code during the CAPTURE_DATA_REGISTER state of the TAP controller and this code can subsequently be shifted out. At board level, this code can be used to verify component manufacturer, type and version number. The device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to TDI) and bit 0 is the least significant bit (nearest to TDO) (see Fig.16). A device identification register is specified in "IEEE Std. 1149.1b-1994". It is a 32-bit register which contains fields for the specification of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and determination of the version number of ICs during field service. The Test Access Port (TAP) controller of an IC should be in the reset state (TEST_LOGIC_RESET) when the IC is in the functional mode. This reset state also forces the instruction register into a functional instruction such as IDCODE or BYPASS. Table 15 BST instructions supported by the SAA7130HL INSTRUCTION BYPASS EXTEST SAMPLE DESCRIPTION This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO when no test operation of the component is required. This mandatory instruction allows testing of off-chip circuitry and board level interconnections. This mandatory instruction can be used to take a sample of the inputs during normal operation of the component. It can also be used to preload data values into the latched outputs of the boundary scan register. This optional instruction is useful for testing when not all ICs have BST. This instruction addresses the bypass register while the boundary scan register is in external test mode. This optional instruction will provide information on the components manufacturer, part number and version number. CLAMP IDCODE handbook, full pagewidth MSB 31 TDI 28 27 0111000100110000 16-bit part number 12 11 00000010101 11-bit manufacturer identification 1 LSB 0 1 TDO 0001 4-bit version code mandatory MHC175 Fig.16 32 bits of identification code. 2002 Apr 23 34 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected together. SYMBOL VDDD VDDA VSS VIA VI(n) VID PARAMETER digital supply voltage analog supply voltage voltage difference between pins VSSA and VSSD input voltage at analog inputs input voltage at pins XTALI, SDA and SCL input voltage at digital I/O stages outputs in 3-state outputs in 3-state; 3.0 V < VDDD < 3.6 V Tstg Tamb Vesd storage temperature ambient temperature electrostatic discharge voltage note 1 note 2 Notes 1. Machine model: L = 0.75 H, C = 200 pF and R = 0 . 2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 34.6 UNIT K/W CONDITIONS MIN. -0.5 -0.5 - -0.5 -0.5 -0.5 -0.5 -65 0 -250 -3500 MAX. +4.6 +4.6 100 +4.6 V V mV V UNIT VDDD + 0.5 V +4.6 +5.5 +150 70 +200 +3500 V V C C V V 2002 Apr 23 35 Philips Semiconductors Product specification PCI video broadcast decoder 11 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD VDDA P digital supply voltage analog supply voltage power dissipation power state D0 for typical application - D0 after reset D1 D2 D3-hot Crystal oscillator fxtal(nom) fxtal(n) fxtal Pdrive tj VIH(XTALI) VIL(XTALI) nominal crystal frequency permissible nominal frequency deviation oscillator frequency range crystal power level of drive at pin XTALO oscillator clock jitter HIGH-level input voltage at pin XTALI LOW-level input voltage at pin XTALI crystal 1; see Table 16 crystal 2; see Table 16 - - - 24 - - 2 -0.3 32.11 - 32.11 0.5 - - - - - - - - 1.0 0.1 0.2 0.1 0.02 - - - - - 3.0 3.0 3.3 3.3 PARAMETER CONDITIONS MIN. TYP. SAA7130HL MAX. UNIT 3.6 3.6 V V W W W W W MHz MHz 24.576 - 70 x 10-6 33 - 100 VDDD + 0.3 +0.8 MHz mW ps V V PCI-bus inputs and outputs VIH VIL ILIH ILIL VOH VOL Ci HIGH-level input voltage LOW-level input voltage HIGH-level input leakage current LOW-level input leakage current HIGH-level output voltage LOW-level output voltage input capacitance at pin PCI_CLK pin IDSEL other input pins SRr SRf output rise slew rate output fall slew rate 0.4 to 2.4 V; note 3 2.4 to 0.4 V; note 3 5 - - 1 1 - - - - - 12 8 10 5 5 pF pF pF V/ns V/ns VI = 2.7 V; note 1 VI = 0.5 V; note 1 IO = -2 mA IO = 3 or 6 mA; note 2 2 -0.5 - - 2.4 - - - - - - - 5.75 +0.8 10 -10 - 0.55 V V A A V V 2002 Apr 23 36 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL tval PARAMETER CLK to signal valid delay CONDITIONS see Fig.17; note 4 bused signals point-to-point signals 2 2 2 - 7 MIN. TYP. - - - - - - - - - 11 12 - 28 - - - - 40 MAX. UNIT ns ns ns ns ns ns ns s ns ton toff tsu float-to-active delay active-to-float delay input set-up time to CLK see Fig.17; note 5 see Fig.17; note 5 see Fig.17; note 4 bused signals point-to-point signals 10 (12) 0 100 - th trst(CLK) trst(off) input hold time from CLK reset active time after CLK stable reset active to output float delay see Fig.17 note 6 notes 5, 6 and 7 I2C-bus interface, compatible to 3.3 and 5 V signalling (pins SDA and SCL) fbit VIL VIH VOL bit frequency rate LOW-level input voltage HIGH-level input voltage LOW-level output voltage note 8 note 8 Io(sink) = 3 mA 0 -0.5 - - - - 400 +0.3VDD(I2C) 0.4 kbits/s V V 0.7VDD(I2C) - VDD(I2C) + 0.5 V Analog video inputs INPUTS (PINS CV0 TO CV4) Iclamp Vi(p-p) Ci cs B dif Gdif LEDC(d) LEDC(i) S/N ENOB clamping current input voltage (peak-to-peak value) input capacitance DC input voltage VI = 0.9 V - note 9 0.375 - fi < 5 MHz at -3 dB; ADC only; note 10 amplifier plus anti-alias filter bypassed amplifier plus anti-alias filter bypassed - - - - - - fi = 4 MHz; anti-alias filter bypassed; AGC = 0 dB fi = 4 MHz; anti-alias filter bypassed; AGC = 0 dB - - 8 0.75 - - 7 2 2 1.4 2 50 8 - 1.07 10 -50 - - - - - - - A V pF 9-BIT ANALOG-TO-DIGITAL CONVERTERS channel crosstalk analog bandwidth differential phase differential gain DC differential linearity error DC integral linearity error signal-to-noise ratio effective number of bits dB MHz deg % LSB LSB dB bit 2002 Apr 23 37 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) and outputs (pins OUT_LEFT and OUT_RIGHT) Vi(nom)(rms) Vi(max)(rms) Vo(max)(rms) Ri Ro RL(AC) CL Voffset(DC) THD + N nominal input voltage (RMS value) maximum input voltage (RMS value) maximum output voltage (RMS value) input resistance output resistance AC load resistance output load capacitance static DC offset voltage total harmonic distortion-plus-noise signal-to-noise ratio Vi = Vo = 1 V (RMS); fi = 1 kHz; bandwidth B = 20 Hz to 20 kHz note 11 THD < 3%; note 12 THD < 3% Vi(max) = 1 V (RMS) Vi(max) = 2 V (RMS) - - - - - 150 10 - - - 200 1 1 145 48 250 - - 10 0.1 - 2 - - - 375 - 12 30 0.3 mV V V k k k nF mV % S/N reference voltage 70 Vo = 1 V (RMS); fi = 1 kHz; "ITU-R BS.468" weighted; quasi peak between any analog input pairs; fi = 1 kHz between left and right of each input pair 60 60 75 - dB ct cs crosstalk attenuation channel separation - - - - dB dB All digital I/Os: GPIO pins and BST test pins (5 V tolerant) PINS GPIO0 TO GPIO23, V_CLK, GPIO25 TO GPIO27, TDI, TDO, TMS, TCK AND TRST VIH VIL ILI IL(I/O) Ci Rpd Rpu VOH VOL HIGH-level input voltage LOW-level input voltage input leakage current I/O leakage current input capacitance pull-down resistance pull-up resistance HIGH-level output voltage LOW-level output voltage 3.3 V signal levels at VDDD 3.3 V I/O at high-impedance VI = VDDD VI = 0 IO = -2 mA IO = 2 mA 2.0 -0.3 - - - - - 2.4 0 - - - - - 50 50 - - 5.5 +0.8 1 10 8 - - VDDD + 0.5 0.4 V V A A pF k k V V Video port outputs (digital video stream from comb filter decoder or scaler) LLC AND LLC2 CLOCK OUTPUT ON PIN V_CLK (see Fig.18) CL Tcy load capacitance cycle time LLC active LLC2 active 2002 Apr 23 38 15 35 70 - - - 50 39 78 pF ns ns Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL PARAMETER duty factor CONDITIONS CL = 40 pF; note 13 LCC active LCC2 active 35 35 - - 15 notes 14 and 15 LLC active LLC2 active 5 15 - - MIN. TYP. - - - - - - - - - 65 65 5 5 MAX. UNIT % % ns ns tr tf CL th rise time fall time 0.4 to 2.4 V 2.4 to 0.4 V VIDEO DATA OUTPUT (WITH RESPECT TO SIGNAL V_CLK) ON PINS GPIO0 TO GPIO17, GPIO22 AND GPIO23 (see Fig.18) load capacitance data hold time 50 - - 28 55 pF ns ns ns ns tPD propagation delay from positive edge of signal V_CLK notes 14 and 15 LLC active LLC2 active Raw DTV/DVB outputs (reuse of video ADCs in DVB/TV applications with TDA8960 and TDA8961 for VSB reception) CLOCK INPUT SIGNAL X_CLK_IN ON PIN GIPIO18 Tcy tr tf CL Tcy tr tf CL th tPD cycle time duty factor rise time fall time note 13 0.8 to 2.0 V 2.0 to 0.8 V 27.8 40 - - - 27.8 CL = 40 pF 0.4 to 2.4 V 2.4 to 0.4 V 40 - - 25 inverted and not delayed; note 14 inverted and not delayed; notes 14 and 16 5 - 37 50 - - - - - - - - - - 333 60 5 5 ns % ns ns CLOCK OUTPUT SIGNAL ADC_CLK ON PIN V_CLK load capacitance cycle time duty factor rise time fall time 25 - 60 5 5 pF ns % ns ns VSB DATA OUTPUT SIGNALS WITH RESPECT TO SIGNAL ADC_CLK load capacitance data hold time propagation delay from positive edge of signal ADC_CLK 50 - 23 pF ns ns TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19) Tcy tr tf cycle time duty factor rise time fall time note 13 0.8 to 2.0 V 2.0 to 0.8 V - 40 - - 333 - - - - 60 5 5 ns % ns ns 2002 Apr 23 39 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DATA AND CONTROL INPUT SIGNALS ON TS-P PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO0 TO GPIO7, GPIO16, GPIO19 AND GPIO22 (see Fig.19) tsu(D) th(D) input data set-up time input data hold time 2 5 - - - - ns ns TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19) Tcy tr tf cycle time duty factor rise time fall time note 13 0.8 to 2.0 V 2.0 to 0.8 V 37 40 - - - - - - - 60 5 5 ns % ns ns DATA AND CONTROL INPUT SIGNALS ON TS-S PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO16, GPIO19, GPIO21 AND GPIO22 (see Fig.19) tsu(D) th(D) Notes 1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs. 2. Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA; these are pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. 4. REQ# and GNT# are point-to-point signals and have different output valid delay and input set-up times than bused signals. GNT# has a set-up time of 10 ns. REQ# has a set-up time of 12 ns. 5. For purposes of active or float timing measurements, the high-impedance or `off' state is defined to be when the total current delivered through the device is less than or equal to the leakage current specification. 6. RST is asserted and de-asserted asynchronously with respect to CLK. 7. All output drivers floated asynchronously when RST is active. 8. VDD(I2C) is the extended pull-up voltage of the I2C-bus (3.3 or 5 V bus). 9. Nominal analog video input signal is to be terminated by 75 that results in 1 V (p-p) amplitude. This termination resistor should be split into 18 and 56 , and the dividing tap should feed the video input pin, via a coupling capacitor of 47 nF, to achieve a control range from -3 dB (attenuation) to +6 dB (amplification) for the internal automatic gain control. See also application notes SAA7130HL/34HL. 10. See the user manuals of the SAA7130HL/34HL for Anti-Alias Filter (AAF). 11. Definition of levels and level setting: a) The full-scale level for analog audio signals VFS = 0.8 V (RMS). The nominal level at the digital crossbar switch is defined at -15 dB (FS). b) Nominal audio input levels: external, mono, Vi = 280 mV (RMS); -9 dB (FS). 12. The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS) and 2 V (RMS), selectable via register setting VSEL0 (LEFT1, RIGHT1) and VSEL1 (LEFT2, RIGHT2). tH 13. The definition of the duty factor: = ------T cy 14. The output timing must be measured with the load of a 30 pF capacitor to ground and a 500 resistor to 1.4 V. 2002 Apr 23 40 input data set-up time input data hold time 2 5 - - - - ns ns Philips Semiconductors Product specification PCI video broadcast decoder 15. Signal V_CLK inverted; not delayed (programming register vp_clk_ctr). 16. tPD = 6 ns + 0.6TADC_CLK in ns (TADC_CLK = 28 ns). SAA7130HL handbook, full pagewidth 2.4 V CLK 1.5 V tval OUTPUT DELAY 1.5 V 0.4 V 3-STATE OUTPUT ton toff tsu INPUT 1.5 V input valid th 2.4 V 1.5 V 0.4 V MGG280 Fig.17 PCI I/O timing. 2002 Apr 23 41 Philips Semiconductors Product specification PCI video broadcast decoder SAA7130HL handbook, full pagewidth t PD th video data and control output (pins GPIO0 to GPIO 17, GPIO 22 and GPIO23) tH tL 2.4 V 0.4 V 2.4 V clock output (pin V_CLK) 1.5 V 0.4 V tf tr MHC002 Fig.18 Data output timing (video data, control outputs and raw DTV/DVB). handbook, full pagewidth and TS data control input (pins GPIO0 to GPIO 7, GPIO 16, GPIO19 and GPIO21) t su(D) t h(D) 2.0 V 0.8 V 2.0 V TS_CLK (pin GPIO20) 1.5 V 0.8 V tr tf MHC003 Fig.19 Data input timing (TS data and control inputs). 2002 Apr 23 42 Philips Semiconductors Product specification PCI video broadcast decoder Table 16 Specification of crystals and related applications (examples); note 1 CRYSTAL FREQUENCY 32.11 MHz FUNDAMENTAL STANDARD Crystal specification Typical load capacitance Maximum series resonance resistance Typical motional capacitance Maximum parallel capacitance Maximum permissible deviation Maximum temperature deviation External components Typical load capacitance at pin XTALI Typical load capacitance at pin XTALO Typical capacitance of LC filter Typical inductance of LC filter Note 1. For oscillator application, see the application notes of the SAA7130HL/34HL. 33 10 15 27 5.6 20 30 20 7 8 60 13.5 3 1 8 50 1.5 4.3 30 x 10-6 30 x 10-6 20 30 20 7 8 60 1 3.3 1B 1C 3rd HARMONIC 1A 24.576 MHz FUNDAMENTAL 2B 2C SAA7130HL UNIT 3rd HARMONIC 2A 10 80 1.5 3.5 50 x 10-6 20 x 10-6 pF fF pF 30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6 30 x 10-6 18 pF 33 10 15 27 5.6 18 pF n.a. n.a. n.a. n.a. 1 4.7 n.a. n.a. n.a. n.a. 1 4.7 nF H 2002 Apr 23 43 Philips Semiconductors Product specification PCI video broadcast decoder 12 PACKAGE OUTLINE LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm SAA7130HL SOT425-1 c y X A 102 103 65 64 ZE e E HE A A2 A 1 (A 3) Lp L detail X wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 0o o 22.15 16.15 21.85 15.85 ISSUE DATE 99-12-27 00-01-19 2002 Apr 23 44 Philips Semiconductors Product specification PCI video broadcast decoder 13 SOLDERING 13.1 Introduction to soldering surface mount packages SAA7130HL If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 13.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 13.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 13.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 2002 Apr 23 45 Philips Semiconductors Product specification PCI video broadcast decoder 13.5 Suitability of surface mount IC packages for wave and reflow soldering methods SAA7130HL SOLDERING METHOD PACKAGE WAVE BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 14 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. not suitable not not not suitable(2) recommended(3)(4) recommended(5) suitable REFLOW(1) suitable suitable suitable suitable suitable Preliminary data Qualification Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 2002 Apr 23 46 Philips Semiconductors Product specification PCI video broadcast decoder 15 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 17 PURCHASE OF PHILIPS I2C COMPONENTS SAA7130HL Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. ICs with MPEG-2 functionality Use of this product in any manner that complies with the MPEG-2 Standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 Steele Street, Suite 300, Denver, Colorado 80206. ICs with MPEG-audio/AC-3 audio functionality Purchase of a Philips IC with an MPEG-audio and/or AC-3 audio functionality does not convey an implied license under any patent right to use this IC in any MPEG-audio or AC-3 audio application. For more information please contact the nearest Philips Semiconductors sales office or e-mail: licensing.cip@philips.com. Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2002 Apr 23 47 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2002 SCA74 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753505/01/pp48 Date of release: 2002 Apr 23 Document order number: 9397 750 08669 |
Price & Availability of SAA7130
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |